I am a Postdoctoral Appointee at the Mathematics and Computer Science Division at Argonne National Laboratory, USA, and a Postdoc-at-Large at the University of Chicago. My research focuses on scalable systems for training and checkpointing large language models (LLMs), with an emphasis on breaking the GPU memory wall through multi-level offloading across heterogeneous memory and storage hierarchies (GPU HBM, host DRAM, CXL, NVMe, parallel file systems). I am particularly interested in designing asynchronous, cache-aware data movement strategies that enable efficient hybrid CPU-GPU training of transformer models at scales exceeding hundreds of billions of parameters, as well as lazy, non-blocking checkpointing techniques that minimize I/O interference during long-running training jobs.

More broadly, my work spans I/O performance optimization for HPC and AI workloads, including GPU-accelerated multi-level checkpoint caching and prefetching for scientific simulations, distributed training parallelism strategies, and data compression pipelines. My research has been recognized with Best Paper awards at HPDC 2024 and HiPC 2022.

I graduated from the Rochester Institute of Technology (RIT) in 2024, under the advisement of Prof. M. Mustafa Rafique and Prof. Bogdan Nicolae (ANL). My Ph.D. thesis received the 2025 ACM SIGHPC Doctoral Dissertation Award Honorable Mention.

I maintain a somewhat up-to-date list of conference and workshop deadlines in the HPC and distributed systems space at this link. Please recheck the official conference webpage for inconsistencies and updates; this is only meant for quick reference.