I am a Postdoctoral Appointee at the Mathematics and Computer Science Division at Argonne National Laboratory, USA, and a Postdoc-at-Large at the University of Chicago. My research focuses on scalable systems for inferencing, training, and checkpointing large transformer-based models, emphasizing breaking the GPU memory wall through throughput- and latency-aware scheduling and multilevel adaptive offloading across heterogeneous memory and storage hierarchies (GPU HBM, host DRAM, CXL, NVMe, parallel file systems). I am particularly interested in designing asynchronous, cache-aware scheduling and data movement strategies that enable efficient hybrid CPU-GPU execution of transformer models spanning hundreds of billions of parameters. More broadly, my work spans I/O performance optimization for HPC and AI workloads, including GPU-accelerated multi-level checkpoint caching and prefetching for scientific simulations, distributed training parallelism strategies, and data compression pipelines. 

I graduated from the Rochester Institute of Technology (RIT) in 2024, under the advisement of Prof. M. Mustafa Rafique and Prof. Bogdan Nicolae (ANL). My work has received Best Paper Awards at HPDC'24 and HiPC'22; my Ph.D. thesis received the 2025 ACM SIGHPC Doctoral Dissertation Award Honorable Mention; and my contributions were honored with a 2026 Argonne Outstanding Postdoc Award.